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C2C rev. ad5220Cspecifications electrical characteristics parameter symbol conditions min typ 1 max units dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a = nc, r ab = 10 k w C1 0.4 +1 lsb r wb , v a = nc, r ab = 50 k w or 100 k w C0.5 0.1 +0.5 lsb resistor nonlinearity 2 r-inl r wb , v a = nc, r ab = 10 k w C1 0.5 +1 lsb r wb , v a = nc, r ab = 50 k w or 100 k w C0.5 0.1 +0.5 lsb nominal resistor tolerance d rt a = +25 c C30 +30 % resistance temperature coefficient d r ab / d tv ab = v dd , wiper = no connect 800 ppm/ c wiper resistance r w i w = v dd /r, v dd = +3 v or +5 v 40 100 w dc characteristics potentiometer divider mode specifications apply to all vrs resolution n 7 bits integral nonlinearity 3 inl r ab = 10 k w C1 0.5 +1 lsb r ab = 50 k w , 100 kw C0.5 0.2 +0.5 lsb differential nonlinearity error 3 dnl r ab = 10 k w C1 0.4 +1 lsb r ab = 50 k w , 100 kw C0.5 0.1 +0.5 lsb voltage divider temperature coefficient d v w / d t code = 40 h 20 ppm/ c full-scale error v wfse code = 7f h C2 C0.5 0 lsb zero-scale error v wzse code = 00 h 0 +0.5 +1 lsb resistor terminals voltage range 4 v a, v b, v w 0v dd v capacitance 5 a, b c a, c b f = 1 mhz, measured to gnd, code = 40 h 10 pf capacitance 5 wc w f = 1 mhz, measured to gnd, code = 40 h 48 pf common-mode leakage i cm v a = v b = v w 7.5 na digital inputs and outputs input logic high v ih v dd = +5 v/+3 v 2.4/2.1 v input logic low v il v dd = +5 v/+3 v 0.8/0.6 v input current i il v in = 0 v or +5 v 1 m a input capacitance 5 c il 5p f power supplies power supply range v dd 2.7 5.5 v supply current i dd v ih = +5 v or v il = 0 v, v dd = +5 v 15 40 m a power dissipation 6 p diss v ih = +5 v or v il = 0 v, v dd = +5 v 75 200 m w power supply sensitivity pss 0.004 0.015 %/% dynamic characteristics 5, 7, 8 bandwidth C3 db bw_10k r ab = 10 k w , code = 40 h 650 khz bw_50k r ab = 50 k w , code = 40 h 142 khz bw_100k r ab = 100 k w , code = 40 h 69 khz total harmonic distortion thd w v a =1 v rms + 2.5 v dc, v b = 2.5 v dc, f = 1 khz 0.002 % v w settling time t s v a = v dd , v b = 0 v, 50% of final value, 10k/50k/100k 0.6/3/6 m s resistor noise voltage e nwb r wb = 5 k w , f = 1 khz 14 nv/ ? hz interface timing characteristics applies to all parts 5, 9 input clock pulsewidth t ch , t cl clock level high or low 25 ns cs to clk setup time t css 20 ns cs rise to clock hold time t csh 20 ns u/ d to clock fall setup time t uds 10 ns notes 1 typicals represent average readings at +25 c and v dd = +5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see figure 29 test circuit. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 28 test circuit. 4 resistor terminals a, b, w have no limitations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 7 bandwidth, noise and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the fastest settling time and highest band- width. the highest r value results in the minimum overall power consumption. 8 all dynamic characteristics use v dd = +5 v. 9 see timing diagrams for location of measured values. all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. switching characteristics are measured using both v dd = +3 v or +5 v. specifications subject to change without notice. (v dd = +3 v 6 10% or +5 v 6 10%, v a = +v dd , v b = 0 v, C40 8 c < t a < +85 8 c unless otherwise noted) a
ad5220 C3C rev. absolute maximum ratings* (t a = +25 c, unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +7 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v dd a x Cb x , a x Cw x , b x Cw x . . . . . . . . . . . . . . . . . . . . . . 20 ma digital input voltage to gnd . . . . . . . . . . . 0 v, v dd + 0.3 v operating temperature range . . . . . . . . . . . C40 c to +85 c maximum junction temperature (t j max) . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c package power dissipation . . . . . . . . . . . . . . (t j maxCt a )/ q ja thermal resistance q ja p-dip (n-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 c/w soic (so-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 c/w m soic (rm-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 c/w *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5220 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 clk u/d a1 gnd v dd cs b1 w1 ad5220 t css t ch t csh t uds t cl 1 0 1 0 1 0 cs clk u/d figure 3. detail timing diagram table i. truth table cs clk u/ d operation l t h wiper increment toward terminal a l t l wiper decrement toward terminal b h x x wiper position fixed pin function descriptions pin no. name description 1 clk serial clock input, negative edge triggered 2u/ d up/down direction increment control 3 a1 terminal a1 4 gnd ground 5 w1 wiper terminal 6 b1 terminal b1 7 cs chip select input, active low 8v dd positive power supply a
ad5220 C4C rev. Ctypical performance characteristics percent of nominal end-to-end resistance C % r ab 100 75 0 0 32 128 64 96 50 25 r wb r wa code C decimal figure 4. wiper to end terminal resistance vs. code code C decimal rdnl C lsb 0.5 C0.5 0 16 128 32 48 64 80 96 112 0.4 0.1 0.0 C0.2 C0.4 0.3 0.2 C0.1 C0.3 t a = +258c v dd = +5.5v 50kv version 10kv version 100kv version figure 7. r-dnl relative resistance step position nonlinearity error vs. code code C decimal dnl C lsb 0.5 C0.5 0 16 128 32 48 64 80 96 112 0.4 0.1 0.0 C0.2 C0.4 0.3 0.2 C0.1 C0.3 50kv version 10kv version 100kv version t a = +258c v dd = +5.5v v a = +5.5v v b = 0v figure 10. potentiometer divider dnl error vs. code conduction current, i wb C ma v wb C v 6 0 0 20 120 40 60 80 100 5 4 3 2 1 v dd = 5.5v r ab = 50kv 7f h 08 h 01 h 02 h 04 h 10 h 20 h 40 h figure 5. resistance linearity vs. conduction current code C decimal rinl C lsb 0.5 C0.5 0 16 128 32 48 64 80 96 112 0.4 0.1 0.0 C0.2 C0.4 0.3 0.2 C0.1 C0.3 t a = +258c v dd = +5.5v 50kv version 10kv version 100kv version figure 8. r-inl resistance non- linearity error vs. supply voltage supply voltage C v potentiometer divider nonlinearity C lsb 0.600 0.000 2.00 2.50 6.00 3.00 3.50 4.00 4.50 5.00 5.50 0.525 0.300 0.255 0.150 0.075 0.450 0.375 code = 40 h r ab = 50kv v a = v dd figure 11. potentiometer divider inl error vs. supply voltage wiper resistance C v frequency 48 24 0 20 40 32 16 8 28 36 44 52 60 ss = 300 units v dd = +2.7v t a = +258c figure 6. wiper contact resistance code C decimal inl C lsb 0.5 C0.5 0 16 128 32 48 64 80 96 112 0.4 0.1 0.0 C0.2 C0.4 0.3 0.2 C0.1 C0.3 t a = +258c v dd = +5.5v v a = +5.5v v b = 0v 50kv version 10kv version 100kv version figure 9. potentiometer divider inl error vs. code temperature C 8c nominal end-to-end resistance C kv 100 80 0 C40 C15 85 10 35 60 60 40 20 100kv version 50kv version 10kv version figure 12. nominal resistance vs. temperature a
ad5220 C5C rev. code C decimal potentiometer mode tempco C ppm/8c 60 C10 0 16 128 32 48 64 80 96 112 53 32 25 11 C3 46 39 18 4 C558c < t a < +858c v dd = +5.5v 50kv and 100kv version 10kv version figure 13. d v wb / d t potentiometer mode tempco (10 k w and 50 k w ) frequency C hz gain C db 6 1k 1m 10k 100k 0 C6 C12 C18 C24 C30 C36 C42 C48 C54 00 h + C 2.5v w a b op42 + C data = 40 h v dd = +5v v in = v a = 100mv rms v b = +2.5v 40 h 20 h 10 h 08 h 04 h 02 h 01 h figure 16. 50 k w gain vs. frequency vs. code v wb v dd = +5.5v v a = +5.5v v b = 0v f = 100khz data 40 h v 3f h 150mv 100mv 50mv 0mv 5v 0v clk time 500ns / div figure 19. midscale transition glitch code C decimal rheostat mode tempco C ppm/8c 60 C10 0 16 128 32 48 64 80 96 112 53 32 25 11 C3 46 39 18 4 C558c < t a < +858c v dd = +5.5v r wb measured v a = no connect 50kv and 100kv version 10kv version figure 14. d r wb / d t rheostat frequency C hz gain C db 6 1k 1m 10k 100k 0 C6 C12 C18 C24 C30 C36 C42 C48 C54 + C 2.5v w a b op42 + C data = 40 h v dd = +5v v in = v a = 100mv rms v b = +2.5v 00 h 20 h 10 h 08 h 04 h 02 h 01 h 40 h figure 17. 100 k w gain vs. fre- quency vs. code frequency C hz thd + noise C % 0.0001 10 t a = +258c v dd = +5.0v offset gnd = +2.5v r ab = 10kv noninverting test ckt 32 inverting test ckt 31 0.001 0.01 0.10 1.00 100 1k 10k 100k figure 20. total harmonic distortion plus noise vs. frequency frequency C hz gain C db 6 1k 1m 10k 100k 0 C6 C12 C18 C24 C30 C36 C42 C48 C54 data = 40 h v dd = +5v v in = v a = 100mv rms v b = +2.5v + C 2.5v w a b op42 + C 40 h 20 h 10 h 08 h 04 h 02 h 01 h 00 h figure 15. 10 k w gain vs. frequency vs. code v wb v dd = +5.5v v a = v b = 0v f = 100khz 20mv/ div time 2ms / div figure 18. digital feedthrough frequency C hz normalized gain flatness C db C5.8 C6.8 10 100 1m C6.3 1k 10k 100k C5.9 C6.0 C6.1 C6.2 C6.4 C6.5 C6.6 C6.7 50kv 10kv data = 40 h v dd = +5v v in = v a = 50mv rms v b = +2.5v 100kv + C 2.5v w a b op42 + C figure 21. normalized gain flatness vs. frequency a
ad5220 C6C rev. 80 0 100k 1k 10k 60 40 20 1m frequency C hz psrr C db v dd = +5v dc 61v p-p ac t a = +258c code = 40 h c l = 10pf v a = 4v, v b = 0v figure 22. power supply rejection vs. frequency temperature C 8c i dd supply current C ma 0.10 0.0001 C40 0.001 C15 10 35 60 85 logic = 0v or v dd v d = +5.5v v dd = +3.3v 0.01 figure 25. supply current vs. tem- perature i dd clock frequency C hz i dd C supply current C ma 400 0 1k 10m 200 10k 100k 1m 350 150 300 100 250 50 data = 3f h v b = 0v t a = +258c v dd = +5.5v v a = +5.5v v dd = +2.7v v a = +2.7v figure 23. i dd supply current vs. clock frequency digital input voltage C v supply current C ma 10 0 1 0.1 0.01 0.001 1.0 2.0 3.0 4.0 5.0 t a = +258c all logic input pins tied together v dd = +5v v dd = +3v figure 26. supply current vs. input logic voltage v b C volts r on C v 80 0 01 6 23 45 60 40 20 t a = +258c see figure 34 for test circuit v dd = +2.7v v dd = +5.5v figure 24. incremental wiper contact resistance vs. v b a
ad5220 C7C rev. v+ dut v ms a b w v+ = v dd 1lsb = v+/128 figure 27. potentiometer divider nonlinearity error test circuit (inl, dnl) no connect i w dut v ms a b w figure 28. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms2 v w i w = v dd /r nominal dut v ms1 a b w r w = [v ms1 C v ms2 ]/i w figure 29. wiper resistance test circuit psrr (db) = 20 log ( CCCCC ) pss (%/%) = CCCCCCC dv ms dv dd dv ms % dv dd % v+ = v dd 10% v dd v a ~ v+ v ms a b w figure 30. power supply sensitivity test circuit (pss, psrr) ~ a b v in 2.5v dc op279 +5v v out dut w offset gnd figure 31. inverting programmable gain test circuit ~ ab v in 2.5v op279 +5v v out dut w offset gnd figure 32. noninverting programmable gain test circuit a b 2.5v dut w offset gnd ~ v in op42 +15v v out C15v figure 33. gain vs. frequency test circuit i sw 0 to v dd r sw = 0.1v i sw code = ?? h 0.1v dut b w figure 34. incremental on resistance test circuit parametric test circuitsC a
ad5220 C8C rev. operation the ad5220 provides a 128-position digitally controlled vari- able resistor (vr) device. changing the vr settings is accom- plished by pulsing the clk pin while cs is active low. the direction of the increment is controlled by the u/ d (up/down) control input pin. when the wiper hits the end of the resistor (terminals a or b) additional clk pulses no longer change the wiper setting. the wiper position is immediately decoded by the wiper decode logic changing the wiper resistance. ap- propriate debounce circuitry is required when push button switches are used to control the count sequence and direction of count. the exact timing requirements are shown in figure 3. the ad5220 powers on in a centered wiper position exhibit- ing nearly equal resistances of r wa and r wb . up/ down cntr rs d e c o d e 7 40 h por en ad5220 v dd a w b gnd clk cs u/d figure 35. block diagram digital interfacing operation the ad5220 contains a three-wire serial input interface. the three inputs are clock (clk), cs and up/down (u/ d ). the negative-edge sensitive clk input requires clean transitions to avoid clocking multiple pulses into the internal up/ down counter register, see figure 35. standard logic families work well. if mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. when cs is taken active low the clock begins to incre- ment or decrement the internal up/down counter dependent upon the state of the u/ d control pin. the up/down counter value (d) starts at 40 h at system power on. each new clk pulse will increment the value of the internal counter by one lsb until the full scale value of 3f h is reached as long as the u/ d pin is logic high. if the u/ d pin is taken to logic low the counter will count down stopping at code 00 h (zero-scale). additional clock pulses on the clk pin are ignored when the wiper is at either the 00 h position or the 3f h position. all digital inputs ( cs , u/ d , clk) are protected with a series input resistor and parallel zener esd structure shown in figure 36. logic 1kv figure 36. equivalent esd protection digital pins 20v a, b, w gnd figure 37. equivalent esd protection analog pins d0 d1 d2 d3 d4 d5 d6 rdac up/down cntr & decode wx bx r s = r nominal /128 r s r s r s ax figure 38. ad5220 equivalent rdac circuit programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b is available with values of 10 k w , 50 k w , and 100 k w . the final three characters of the part number determine the nominal resistance value, e.g., 10 k w =10; 50 k w = 50; 100 k w = 100. the nominal resistance (r ab ) of the vr has 128 contact points accessed by the wiper terminal, plus the b terminal contact. at power on the resistance from the wiper to either end terminal a or b is approximately equal. clocking the clk pin will in- crease the resistance from the wiper w to terminal b by one unit of r s resistance (see figure 38). the resistance r wb is determined by the number of pulses applied to the clock pin. each segment of the internal resistor string has a nominal resis- tance value of r s = r ab /128, which becomes 78 w in the case of the 10 k w ad5220bn10 product. care should be taken to limit the current flow between w and b in the direct contact state to a maximum value of 5 ma to avoid degradation or possible de- struction of the internal switch contact. like the mechanical potentiometer the rdac replaces, it is totally symmetrical (see figure 38). the resistance between the wiper w and terminal a also produces a digitally controlled resistance r wa . when these terminals are used the bCterminal should be tied to the wiper. the typical part-to-part distribution of r ba is process lot depen- dent having a 30% variation. the change in r ba with tempera- ture has a 800 ppm/ c temperature coefficient. the r ba temperature coefficient increases as the wiper is pro- grammed near the b-terminal due to the larger percentage con- tribution of the wiper contact switch resistance, which has a 0.5%/ c temperature coefficient. figure 14 shows the effect of the wiper contact resistance as a function of code setting. an- other performance factor influenced by the switch contact resis- tance is the relative linearity error performance between the 10 k w , and the 50 k w or 100 k w versions. the same switch contact resistance is used in all three versions. thus the perfor- mance of the 50 k w and 100 k w devices which have the least impact on wiper switch resistance exhibits the best linearity error, see figures 7 and 8. a
ad5220 C9C rev. programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example connecting a terminal to +5 v and b terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 lsb less than +5 v. each lsb of voltage is equal to the voltage applied across terminals ab divided by the 128-position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to termi- nals ab is: v w ( d ) = d /128 v ab + v b (1) d represents the current contents of the internal up/down counter. operation of the digital potentiometer in the divider mode re- sults in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors, not the absolute value, therefore, the drift improves to 20 ppm/ c. applications information the negative-edge sensitive clk pin does not contain any internal debounce circuitry. this standard cmos logic input responds to fast negative edges and needs to be debounced externally with an appropriate circuit designed for the type of switch closure device being used. good performance results at the clk input pin when the negative logic transition has a minimum slew rate of 1 v/ m s. a wide variety of standard circuits can be used such as a one-shot multivibrator, schmitt triggered gates, cross coupled flip-flops, or rc filters to drive the clk pin with uniform negative edges. this will prevent the digital potentiometer from skipping output codes while counting due to switch contact bounce. a
ad5220 -10- rev. a outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 39. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 40. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 41. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad5220 rev. a -11- ordering guide model 1, 2, 3 r ab (k) temperature range package description package option branding ad5220bnz10 10 ?40c to +85c 8-lead pdip n-8 ad5220bnz100 100 ?40c to +85c 8-lead pdip n-8 ad5220bnz50 50 ?40c to +85c 8-lead pdip n-8 ad5220br10 10 ?40c to +85c 8-lead soic_n r-8 ad5220br10-reel7 10 ?40c to +85c 8-lead soic_n r-8 ad5220br100 100 ?40c to +85c 8-lead soic_n r-8 ad5220br100-reel 100 ?40c to + 85c 8-lead soic_n r-8 ad5220br100-reel7 100 ?40c to +85c 8-lead soic_n r-8 ad5220brz10 10 ?40c to +85c 8-lead soic_n r-8 ad5220brz10-reel 10 ?40c to +85c 8-lead soic_n r-8 ad5220brz10-reel7 10 ?40c to +85c 8-lead soic_n r-8 ad5220wbrz10-reel7 10 ?40c to +85c 8-lead soic_n r-8 ad5220brz100 100 ?40c to +85c 8-lead soic_n r-8 ad5220brz100-reel7 100 ?40c to +85c 8-lead soic_n r-8 ad5220brz50 50 ?40c to +85c 8-lead soic_n r-8 ad5220brm100 100 ?40c to +85c 8-lead msop rm-8 dqc AD5220BRM100-REEL7 100 ?40c to +85c 8-lead msop rm-8 dqc ad5220brmz10 10 ?40c to +85c 8-lead msop rm-8 d9h ad5220brmz10-reel7 10 ?40c to +85c 8-lead msop rm-8 d9h ad5220brmz100 100 ?40c to +85c 8-lead msop rm-8 #dqc ad5220brmz100-r7 100 ?40c to +85c 8-lead msop rm-8 #dqc ad5220brmz50 50 ?40c to +85c 8-lead msop rm-8 #dqb ad5220brmz50-rl7 50 ?40c to +85c 8-lead msop rm-8 #dqb 1 z = rohs compliant part. 2 the ad5220 die size is 37 mil 54 mil, 1998 sq mil; 0.938 mm 1.372 mm, 1.289 sq mm. contains 754 transistors. patent number 5495245 applies. 3 w = qualified for automotive products. automotive products the ad5220w models are available with controlled manufacturing to support the quality and reliability requirements of automotiv e applications. note that these automotive models may have specifications that differ from the commercial models; therefore desig ners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. revision history 12/10rev. 0 to rev. a changes to features section ........................................................... 1 updated outline dimensions ....................................................... 10 changes to ordering guide .......................................................... 11 added automotive products section .......................................... 11 10/98revision 0: initial version ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03426-0-12/10(a)

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